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An Accumulator—Based Test-Per-Clock SchemeMAGOS, Dimitrios; VOYIATZIS, Ioannis; TARNICK, Steffen et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 6, pp 1090-1094, issn 1063-8210, 5 p.Article

Theoretical properties of LFSRs for built-in self testDUFAZA, C.Integration (Amsterdam). 1998, Vol 25, Num 1, pp 17-35, issn 0167-9260Article

A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault DetectionKIM, Moonjoon; LEE, Jeongmin; HONG, Wongi et al.Lecture notes in computer science. 2006, pp 577-583, issn 0302-9743, isbn 3-540-34070-X, 7 p.Conference Paper

Functionality fault model : A basis for technology-specific test generationZEMVA, A; ZAJC, B.Microelectronics and reliability. 1998, Vol 38, Num 4, pp 597-604, issn 0026-2714Article

Accumulator Based 3-Weight Pattern GenerationPASCHALIS, Antonis; VOYIATZIS, Ioannis; GIZOPOULOS, Dimitris et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 2, pp 357-361, issn 1063-8210, 5 p.Article

A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan designLIN, Shih-Ping; LEE, Chung-Len; CHEN, Jwu-E et al.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 7, pp 767-776, issn 1063-8210, 10 p.Article

Theory of wire addition and removal in combinational Boolean networks : On VLSI design and testCHANG, Chih-Wei; MAREK-SADOWSKA, Malgorzata.Microelectronic engineering. 2007, Vol 84, Num 2, pp 229-243, issn 0167-9317, 15 p.Article

Pattern matching assisted modeling test pattern generationLE HONG; QIAO LI; JIAN RAO et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7274, issn 0277-786X, isbn 978-0-8194-7527-5 0-8194-7527-0, 727429.1-727429.0, 2Conference Paper

Test generation for technology-specific multi-faults based on detectable perturbationsZEMVA, Andrej; ZAJC, Baldomir.Microelectronics and reliability. 2005, Vol 45, Num 1, pp 163-173, issn 0026-2714, 11 p.Article

Efficient identification of crosstalk induced slowdown targetsBREUER, Melvin A; GUPTA, Sandeep K; NAZARIAN, Shahin et al.Asian test symposium. 2004, pp 124-131, isbn 0-7695-2235-1, 1Vol, 8 p.Conference Paper

A hybrid-type test pattern generating mechanismCHEN, Chuen-Yau; HSU, An-Chi.IEEE International Symposium on Circuits and Systems. 2004, pp 225-228, isbn 0-7803-8251-X, 4 p.Conference Paper

Approximate equivalence verification for protocol interface implementation via Genetic AlgorithmsCORNO, F; SONZA REORDA, M; SQUILLERO, G et al.Lecture notes in computer science. 1999, pp 182-192, issn 0302-9743, isbn 3-540-65837-8Conference Paper

Cellular automata for weighted random pattern generationNEEBEL, D. J; KIME, C. R.IEEE transactions on computers. 1997, Vol 46, Num 11, pp 1219-1229, issn 0018-9340Article

Test vector generation and classification using FSM traversalsMARCZYNSKI, Ralph; THORNTON, Mitchell A; SZYGENDA, Stephen A et al.IEEE International Symposium on Circuits and Systems. 2004, pp 309-312, isbn 0-7803-8251-X, 4 p.Conference Paper

Weighted pseudo-random BIST for N-detection of single stuck-at faultsCHAOWEN YU; REDDY, Sudhakar M; POMERANZ, Irith et al.Asian test symposium. 2004, pp 178-183, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper

Verifying properties using sequential ATPGABRAHAM, Jacob A; VEDULA, Vivekananda M; SAAB, Daniel G et al.Proceedings - International Test Conference. 2002, pp 194-202, issn 1089-3539, isbn 0-7803-7542-4, 9 p.Conference Paper

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring countersCHAKRABARTY, Krishnendu; MURRAY, Brian T; IYENGAR, Vikram et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 633-636, issn 1063-8210Conference Paper

Testing iterative logic arrays for sequential faults with a constant number of patternsCHIH-YUANG SU; CHENG-WEN WU.IEEE transactions on computers. 1994, Vol 43, Num 4, pp 495-501, issn 0018-9340Article

Net integrity checking by optical localization techniquesHALLER, G; MACHOUAT, A; LEWIS, D et al.Microelectronics and reliability. 2009, Vol 49, Num 9-11, pp 1175-1181, issn 0026-2714, 7 p.Conference Paper

Shift register based TPG for at-speed interconnect BISTJUTMAN, A.International conference on microelectronics. 2004, isbn 0-7803-8166-1, 2Vol, vol 2, 751-754Conference Paper

Efficient path delay testing using scan justificationHUH, Kyung-Hoi; KANG, Yong-Seok; KANG, Sungho et al.ETRI journal. 2003, Vol 25, Num 3, pp 187-194, issn 1225-6463, 8 p.Article

Design rewiring using ATPGVENERIS, Andreas; ABADIR, Magdy S; AMIRI, Mandana et al.Proceedings - International Test Conference. 2002, pp 223-232, issn 1089-3539, isbn 0-7803-7542-4, 10 p.Conference Paper

Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSRHUANG, L.-R; JOU, J.-Y; KUO, S.-Y et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 9, pp 1015-1024, issn 0278-0070Article

An optimized DFT and test pattern generation strategy for an intel high performance microprocessorWU, David M; MIKE LIN; REDDY, Madhukar et al.International Test Conference. 2004, pp 38-47, isbn 0-7803-8580-2, 1Vol, 10 p.Conference Paper

Interconnect test pattern generation algorithm for meeting device and global sso limits with safe initial vectorsBAKER, Kendrick; NOURANI, Mehrdad.International Test Conference. 2004, pp 163-172, isbn 0-7803-8580-2, 1Vol, 10 p.Conference Paper

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